1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, such as an IC chip, and more particularly to a method of manufacturing a semiconductor device, including a forming process of a so-called contact hole formed to pass through an insulating film and open above the semiconductor substrate.
2. Prior Art
The forming process of contact holes is one of the processes involved in the manufacture of integrated circuits, including IC chips. The contact hole is formed as an empty area which passes through an insulating film covering a semiconductor substrate, for example, and opens above the semiconductor substrate, and in this empty area an electrode path can be provided.
The contact hole described above can be formed by an etching technique using a photolithographically delineated resist pattern as the mask. Meanwhile, to meet a growing demand for higher density devices, there is a newly proposed SAC method for forming a contact hole by a self-aligned technique.
According to this method of forming a self-aligned contact hole, for example, which is open above the semiconductor substrate between a pair of gates, are formed in the insulating film covering the pair of gates formed on the semiconductor substrate separated apart from each other.
By this method of forming a self-aligned contact hole, an etching stopper film having electrical insulating properties is formed to cover the pair of gates on the semiconductor substrate and the exposed surfaces of the semiconductor substrate. Then, an insulating film is deposited to have the pair of gates and the etching stopper film covering the gates embedded in it.
Subsequently, by an etching technique using a lithographically-formed resist pattern as the mask, a preliminary opening is formed to have partially exposed an etching stopper film which covers an area between a pair of gates where a contact hole is to be formed. That portion of the etching stopper film which is exposed on the semiconductor substrate is removed by a self-aligned method, that is, directly by dry etching with a plasma gas without using a mask.
By this self aligned method, the preliminary opening can be formed appropriately in the insulating film without causing a substantial damage to the etching stopper film by performing etching with an etching gas which shows a higher etch rate of the insulating film covering the etching stopper film than the etch rate of the etching stopper film, in other words, by performing etching with such an etching gas as shows a large selectivity ratio of the insulating film to the etching stopper film in the forming process of the preliminary opening.
Therefore, by subsequent dry etching of the etching stopper film without a mask, a minute opening can be formed without the need to consider design allowances for mask positioning, so that this method can conform to geometrical design rules so tight as a unit spacing of 0.25 micron.
However, with an etching gas used to partially expose the etching stopper film by forming the preliminary opening in the insulating film, the insulating film/etching stopper film selectivity is no more than 20 or so. Therefore, during etching to form the preliminary opening, the etching stopper film, too, is liable to be damaged by the etching gas.
For this reason, when the predetermined preliminary opening is formed, the gates should be covered with the etching stopper film which serves as electrical protection means, and if the etching step is not finished before the etching stopper film suffers a substantial damage, there is a possibility that the gates under the etching stopper film are exposed.
This exposure of the gates leads to a short circuit between the electrode to be formed in the contact hole and the exposed gate. To prevent a short circuit, the etching work to form the preliminary opening needs to be terminated without fail before the etching stopper film suffers a considerable damage. Consequently, in the conventional semiconductor device manufacturing method including the contact hole forming step using a self-aligned technique has been difficult because meticulous care is indispensable for management of the etching process.
With the progressive microminiaturization of the patterns due to the increasing device integration, while the aspect ratio, that is, the ratio of the depth to the bore diameter of the contact hole becomes larger, the etch rate of the insulating film in the contact hole portion slows down by the microloading effect, so that the insulating film/etching stopper film selectivity of the etching gas further decreases. The result is that the etching stopper film is more liable to be damaged during the formation of the preliminary opening.